1. Field of the Invention
The present invention relates to a sequential circuit which has a function of holding data in a sleep mode.
2. Description of the Related Art
Semiconductor integrated logic circuits are commonly provided with a system including a transistor circuit which makes a high speed operation in an active mode and low power consumption in a sleep mode possible. In particular, the system has a data holding function for protecting stored data in a sequential circuit from being destroyed during a sleep mode. For example, in Japanese Patent No. 2631335 is disclosed the technique of making a high speed operation possible and of supplying electric power via transistors with higher threshold voltages to shut off a leakage current in the sleep mode. Especially, the technique of a sequence circuit is disclosed in which the electric power is directly supplied and a bi-directional circuit composed of higher threshold voltage transistors is added to shut off the leakage current in the sleep mode and to simultaneously protect stored data from being destroyed.
FIG. 1 is a circuit diagram illustrating a conventional semiconductor integrated logic circuit including a sequential circuit, which has a function of holding data in the sleep mode. As shown in FIG. 1, a control transistor HP1I of a p-channel MOSFET of a higher threshold voltage is connected at its source electrode to a higher potential side actual power supply line VDD and at its drain electrode to a higher potential side quasi power supply line VDDV. In response to a sleep mode switching signal SL received at its gate electrode, the control transistor HP1I electrically connects or disconnects the higher potential side actual power supply line to and from the quasi power supply line. Also, another control transistor HN1I of an n-channel MOSFET of a higher threshold voltage is connected at its source electrode to a low potential side actual power supply line GND and at its drain electrode with a lower potential side quasi power supply line GNDV. In response to an inverted sleep mode switching signal SLB received at its gate electrode, the control transistor HN1I electrically connects or disconnects the lower potential side actual power supply line to and from the quasi power supply line. The inverted sleep mode switching signal SLB is a signal obtained by inverting the sleep mode switching signal SL. The sleep mode switching signal SL and inverted sleep mode switching signal SLB are supplied from a sleep mode control circuit (not shown).
A CMOS circuit section composed of lower threshold voltage transistors includes inverter circuits INV1I and INV2I. More particularly, each of the inverter circuits INV1I and INV2I is composed of a p-channel MOSFET of a lower threshold voltage and an n-channel MOSFET of a lower threshold voltage. The gate electrodes of the two transistors are connected to each other as a common input terminal and the drain electrodes of the same are connected to each other as a common output terminal. The source electrodes of the lower threshold voltage p-channel MOSFETs in the inverter circuits INV1I and INV2I are connected to the higher potential side quasi power supply line VDDV. The source electrodes of the lower threshold voltage n-channel MOSFETs in the inverter circuits INV1I and INV2I are connected to the lower potential side quasi power supply line GNDV.
A latch circuit 10 shown in FIG. 1 will be now explained. The CMOS latch circuit 10 is composed of higher threshold voltage transistors, two transfer gates TM1 and TM2, three inverter circuits INV1, INV2, and INV3, and two higher threshold voltage control transistors HP1 and HN1 for shutting off sub-threshold leakage currents.
The inverter circuit INV1 performs buffering of a data signal D supplied to the latch circuit 10 and is composed of a p-channel MOSFET of a lower threshold voltage and an n-channel MOSFET of a lower threshold voltage. The gate electrodes of the two transistors are connected to each other as a common input terminal for receiving the data signal D and the drain gates of the same connected to each other as a common output terminal.
The control transistor HP1 is composed of a p-channel MOSFET of a higher threshold voltage and is connected at its source electrode to the higher potential side actual power supply line VDD. In response to the sleep mode switching signal SL received at its gate electrode, the switching of the control transistor HP1 is controlled. The control transistor HN1 is composed of an n-channel MOSFET of a higher threshold voltage and is connected at its source electrode to the lower potential side actual power supply line GND. In response to the inverted sleep mode switching signal SLB received at its gate electrode, the switching of the control transistor HN1 is controlled. The source electrode of the lower threshold voltage p-channel MOSFET of the inverter circuit INV1 is connected to the drain electrode of the control transistor HP1. Similarly, the source electrode of the lower threshold voltage n-channel MOSFET of the inverter circuit INV1 is connected to the drain electrode of the control transistor HN1.
The transfer gate TM1 is composed of a p-channel MOSFET of a lower threshold voltage and an n-channel MOSFET of a lower threshold voltage. The source electrode of one transistor is joined to the drain electrode of the other, forming a parallel connection. One of the two joints is connected an output terminal of the inverter circuit INV1 and the other serves as an output of the latch circuit 10 for outputting a latch output signal QB to the succeeding stage.
A clock signal .phi. is applied to the gate electrode of the lower threshold voltage n-channel MOSFET of the transmission circuit TM1 while an inverted clock signal *.phi. which is an inverted form of the clock signal .phi. is applied to the gate electrode of lower threshold voltage p-channel MOSFET.
The transfer gate TM2 is substantially identical in the circuitry construction to the transfer gate TM1 and connected at one of its bi-directional electrodes to the input terminal of the inverter circuit INV3 and at the other to the output terminal of the inverter circuit INV2. The transfer gate TM2 may be composed of MOSFETs of either a low or a higher threshold voltage.
The inverter circuits INV2 and INV3 are substantially identical in the circuitry construction to the inverter circuit INV1. While the inverter circuit INV1 is composed of the lower threshold voltage MOSFETs, higher threshold voltage MOSFETs are used in the inverter circuits INV2 and INV3. The inverter circuit INV3 receives the latch output signal QB of the latch circuit 10 as an input signal, unlike the inverter circuit INV1. The inverter circuit INV3 is connected directly between the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND, without passing through the control transistor HP1 as the higher threshold voltage p-channel MOSFET and the control transistor HN1 as the higher threshold voltage n-channel MOSFET. The output of the inverter circuit INV3 is connected to the input of the inverter circuit INV2. The inverter circuit INV2, like the inverter circuit INV3, is corrected directly between the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND.
The operation of the latch circuit 10 shown in FIG. 1 will be described as a sequential circuit having a function of holding data in the sleep mode.
In particular, the inverted data signal D produced by the inverter circuit INV1 is taken at the timing of the clock signal .phi. and the inverted clock signal *.phi. supplied to the transfer gate TM1 and outputted as the output QB of the latch circuit 10 to the succeeding stage. The inverted data signal from the inverter circuit INV1 is received by the transfer gate TM1 only when the sleep mode switching signal SL and the inverted sleep mode switching signal SLB allow the inverter circuit INV1 to be connected to the power supply.
The output signal QB is also transmitted to the inverter circuit INV3 of which the output is connected to the inverter circuit INV2. The transfer gate TM2 transfers the output signal of the inverter circuit INV2 to the input terminal of the inverter circuit INV3 based on the clock signal .phi. and the inverted clock signal *.phi. such that the data signal is latched.
When the active mode is set while the sleep mode switching signal SL is in a low level (SL="0") and the inverted sleep mode switching signal SLB is in a high level (SLB="1"), the control transistors HP1 and HN1 are set to the conductive state. As a result, the semiconductor integrated logic device functions as a high speed latch circuit by the transistors of the inverter circuits INV1, INV2, and INV3 and of the transfer gates TM1 and TM2. In contrast, when the sleep mode switching signal SL is shifted to a high level (SL="1") and the inverted sleep mode switching signal SLB is shifted to a low level (SLB="0"), the control transistors HP1 and HN1 become non-conductive. Therefore, the power supply to the inverter circuit INV1 is stopped. The case is supposed that the sleep mode is initiated (SL="1", SLB="0") while the clock signal .phi. is maintained at the low level (.phi.="0") and the inverted clock signal *.phi. is maintained at the high level (*.phi.="1"). In this case, the bistable circuit constructed by the inverter circuits INV2 and INV3 and the transfer gate TM2 can hold the data and the latched data is not destroyed.
Also, in the sleep mode (SL="1", SLB="0"), the inverter circuit INV1 of the lower threshold voltage transistors is disconnected from the voltage supply lines VDD and GND by the higher threshold voltage control transistors HP1 and HN1. Therefore, an increase in the power consumption due to the sub-threshold voltage leakage can be avoided. Also, although the inverter circuits INV2 and INV3 connected directly to the power supply, there is no increase of the power consumption resulting from the sub-threshold voltage leakage in the sleep mode, because the inverter circuits INV2 and INV3 include the higher threshold voltage transistors.
The inverter circuit INV1 is a primary component of the sequential circuit, shown in FIG. 1, and has a function of holding data in the sleep mode and serves as a buffer for the data signal D. For this inverter circuit INV1, two higher threshold voltage switching elements may be used. That is, the control transistor HP1 of the higher threshold voltage p-channel MOSFET and the control transistor HN1 of the higher threshold voltage n-channel MSOFET need to be provided at both sides of the inverter circuit INV1 for connection to the higher potential side actual power supply line VDD and the lower potential side actual power supply line GND, respectively. Thus, excess higher threshold voltage transistors need to be provided.
Referring back to FIG. 1, it is supposed that the sleep mode (SL="1", SLB="0") is set when the output of the inverter circuit INV2 is "1", the output of the inverter circuit INV3 is "0", the clock signal .phi. is set to the low level (.phi.="0") and the inverted clock signal *.phi. is set to the high level (*.phi.="1"). In this case, the inverter circuit INV2 having the input of "0" and the output of "1" functions a leakage current source. The leakage current passes through the transfer gate TM2 in the conductive state, the transfer gate TM1 composed of the lower threshold voltage transistors in the non-conductive state, and the n-channel MOSFET in the inverter circuit INV1 composed of the lower threshold voltage transistors. Thus, the inverter circuit INV2 functions a sub-threshold leakage current source to the lower potential side actual power supply line GND. However, the control transistor HN1 of the higher threshold voltage n-channel MOSFET is set to the non-conductive state in response to the inverted sleep mode switching signal SLB. Therefore, the sub-threshold voltage leakage current is shut off by the transistor HN1.
Also, it is supposed that the sleep mode (SL="1", SLB="0") is set when the output of the inverter circuit INV2 is "0", the output of the inverter circuit INV3 is "1", the clock signal .phi. is maintained at its low level (.phi.="0") and the inverted clock signal *.phi. is maintained at its high level (*.phi.="1"). In this case, the inverter circuit INV2 having the input of "1" and the output of "0" functions as a leakage current source. The leakage current passes through the transfer gate TM2 in the conductive state, the transfer gate TM1 composed of the lower threshold voltage transistors in the non-conductive state, and the p-channel MOSFET composed of the lower threshold voltage transistor. Thus, the inverter circuit INV2 functions a sub-threshold leakage current source to the higher potential side actual power supply line VDD. However, the control transistor HP1 of the higher threshold voltage p-channel MOSFET is set in the non-conductive state in response to the sleep mode switching signal SL. Therefore, the sub-threshold voltage leakage current is shut off by the higher threshold voltage p-channel MOSFET HP1.
Moreover, the higher potential side actual power supply line VDD functions as a leakage current source. In this case, it could be considered that a leakage current path composed of the p-channel MOSFET in the inverter circuit INV1 composed of the lower threshold voltage transistor in the conductive or non-conductive state and the n-channel MOSFET in the inverter circuit INV1 composed of the lower threshold voltage transistor in the conductive or non-conductive state. Thus, the lower potential side actual power supply line GND functions as the leakage current demanding source. However, the control transistor HP1 of the higher threshold voltage p-channel MOSFET is provided between the p-channel MOSEFT in the inverter circuit INV1 and the higher potential side actual power supply line VDD to be set in the non-conduction state in response to the sleep mode switching signal SL. Therefore, the sub-threshold voltage leakage current can be shut off. In addition, the control transistor HN1 of the higher threshold voltage n-channel MOSFET is provided between the n-channel MOSEFT in the inverter circuit INV1 and the lower potential side actual power supply line GND to be set in the non-conduction state in response to the inverted sleep mode switching signal SLB. Therefore, the sub-threshold voltage leakage current can be shut off.
As described above, the latch circuit 10 in the conventional sequential circuit which has a function of holding data in the sleep mode needs to have the higher threshold voltage switching devices disposed between the inverter circuit INV1 and the higher potential side power supply line VDD and between the inverter circuit INVL and the lower potential side actual power supply line GND. Thus, the shutting off of the sub-threshold voltage leakage current is realized. This will increase the number of components required for the sequential circuit.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-54693). In this reference, when a power is turned on, a fault address determining circuit (30) generates a redundancy determination signal YR and a fault address (A30). A Y address decoder (24) decodes the fault address (A30) to supply the decoding result to a transfer gate (23) and a redundancy latch circuit (32) which is provided for fault bit line pair (BL1a, BL1b). Thus, the redundancy latch circuit (32) is selected to set switches (33a, 33b) to an off state while the power is turned on. Therefore, a leakage current can be prevented from flowing to a word line (WL1) through the fault bit line pair (BL1a, BL1b) and a memory cell (1--1). In this way, increase of power consumption due to a short-circuit between bit lines and between word lines can be prevented.
Also, a static type transfer gate sequential circuit is disclosed in Japanese Laid Open Patent Applications (JP-A-Heisei 5-122020 and JP-A-Heisei 5-122021). In these references, the static type transfer gate sequential circuit is connected between CMOS logic circuits and is composed of a transfer gate (TG), two inverters (V1, V2), an input terminal (D), an output terminal (QB), and a clock input terminal (CC). One of terminals of the transfer gate (TG) is connected to the input terminal (D), and the other terminal is connected to an input terminal of the inverter (V1). The output terminal of the inverter (V1) is connected to the output terminal (QB) and the input terminal of the inverter (V2) whose output terminal is connected to the input terminal of the inverter (V1). In this reference, a resistance value in the signal path is adjusted in the viewpoint of the operation speed. In this way, the static type transfer gate sequential circuit can operate at same high speed as that of a dynamic type, as well as can cope with a low speed operation.
Also, a logic circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-29834). In this reference, a lower threshold voltage logic circuit is connected between a higher potential side quasi power supply line and a lower potential side quasi power supply line. A higher potential side actual power supply line and a lower potential side actual power supply line are connected to the higher potential side quasi power supply line and the lower potential side quasi power supply line through higher threshold voltage transistors (TS1 and TS2), respectively.
Also, a D-type flip-flop circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-202647). In this reference, a CMOS transfer gate for feeding back in the flip-flop circuit is not used. The CMOS flip-flop circuit is connected to a higher potential side power supply line and a lower potential side power supply line via a p-channel MOS transistor and an n-channel MOS transistor.